A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS

Andrew Nicholson; Julian Jenkins; Astria Nur Irfansyah; Nonie Politi; André van Schaik; Tara Julia Hamilton; Torsten Lehmann

doi:10.1109/ISCAS.2013.6572222

A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS

Andrew Nicholson, Julian Jenkins, Astria Nur Irfansyah, Nonie Politi, André van Schaik, Tara Julia Hamilton, Torsten Lehmann

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

10 Citations (Scopus)

Abstract

We present a standard pipelined ADC design using Nauta structure differential op-amps as an alternative to traditional analog op-amps. The six stage pipelined ADC is capable of running at 100MS/s and achieves 8 bit resolution under simulations. The research is focused on the path to scaling to deep sub-micron CMOS and finding alternatives to the reduced gain and low output voltage swing of traditional analog op-amp designs. The Nauta structure op-amp allows us to produce one of the smallest reported areas for a 180nm pipelined ADC occupying only 0.3mm2 for a 10 bit 100MS/s pipelined ADC.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China
Publisher	IEEE
Pages	1833-1836
Number of pages	4
ISBN (Print)	9781467357609
DOIs	https://doi.org/10.1109/ISCAS.2013.6572222
Publication status	Published - 2013
Event	IEEE International Symposium on Circuits and Systems - Duration: 19 May 2013 → …

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Name
ISSN (Print)	0271-4302

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Conference	IEEE International Symposium on Circuits and Systems
Period	19/05/13 → …

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Nicholson, A., Jenkins, J., Irfansyah, A. N., Politi, N., Schaik, A. V., Hamilton, T. J., & Lehmann, T. (2013). A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS. In Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China (pp. 1833-1836). IEEE. https://doi.org/10.1109/ISCAS.2013.6572222

@inproceedings{65280ca26d7c4e74881611e1bf717b6c,

title = "A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS",

abstract = "We present a standard pipelined ADC design using Nauta structure differential op-amps as an alternative to traditional analog op-amps. The six stage pipelined ADC is capable of running at 100MS/s and achieves 8 bit resolution under simulations. The research is focused on the path to scaling to deep sub-micron CMOS and finding alternatives to the reduced gain and low output voltage swing of traditional analog op-amp designs. The Nauta structure op-amp allows us to produce one of the smallest reported areas for a 180nm pipelined ADC occupying only 0.3mm2 for a 10 bit 100MS/s pipelined ADC.",

author = "Andrew Nicholson and Julian Jenkins and Irfansyah, {Astria Nur} and Nonie Politi and Schaik, {Andr{\'e} van} and Hamilton, {Tara Julia} and Torsten Lehmann",

year = "2013",

doi = "10.1109/ISCAS.2013.6572222",

language = "English",

isbn = "9781467357609",

publisher = "IEEE",

pages = "1833--1836",

booktitle = "Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 19-05-2013",

}

Nicholson, A, Jenkins, J, Irfansyah, AN, Politi, N, Schaik, AV, Hamilton, TJ & Lehmann, T 2013, A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS. in Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China. IEEE, pp. 1833-1836, IEEE International Symposium on Circuits and Systems, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6572222

A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS. / Nicholson, Andrew; Jenkins, Julian; Irfansyah, Astria Nur et al.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China. IEEE, 2013. p. 1833-1836.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

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AU - Hamilton, Tara Julia

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AB - We present a standard pipelined ADC design using Nauta structure differential op-amps as an alternative to traditional analog op-amps. The six stage pipelined ADC is capable of running at 100MS/s and achieves 8 bit resolution under simulations. The research is focused on the path to scaling to deep sub-micron CMOS and finding alternatives to the reduced gain and low output voltage swing of traditional analog op-amp designs. The Nauta structure op-amp allows us to produce one of the smallest reported areas for a 180nm pipelined ADC occupying only 0.3mm2 for a 10 bit 100MS/s pipelined ADC.

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A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS

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