@inproceedings{75f0358994894371aee3e88d96ce1407,
title = "A 1.2V 2-bit phase interpolator for 65nm CMOS",
abstract = "We present a digital phase interpolator (PI) design for 65nm CMOS that avoids conventional analog structures, accurately achieves 2-bits phase resolution across a range of rise time and input delays from trise: 48ps {\^a}†{\textquoteright} 200ps using a ratio trise/tdelay of at least 1 or greater. Increased accuracy is available for certain rise times using ratios increasing between 1 and 10 as verified by simulations across process corners using extracted parasitic capacitances but ignoring MOSFET mismatch effects. Power consumption was estimated at 30nW/MHz {\^a}†{\textquoteright} 38nW/MHz across a range of process variation corners in these operating conditions. Monte Carlo simulations across process and MOSFET mismatch conditions show large variations in estimated accuracy. Monte Carlo trials show the PI achieves a worst case DNL error (mean{\~A}‚{\^A}±3{\"I}ƒ) of 1.06 LSB using trise/tdelay ratio of 5.3 and 48ps rise time, and a worst case DNL error (mean {\~A}‚{\^A}±2{\"I}ƒ) of 0.49 LSB for trise/tdelay ratio of 4 and 84ps rise time.",
keywords = "Monte Carlo method, digital-to-time converters, metal oxide semiconductors, complementary, phase interpolation, phase interpolators",
author = "Andrew Nicholson and Julian Jenkins and Schaik, {Andr{\'e} van} and Hamilton, {Tara Julia} and Torsten Lehmann",
year = "2012",
doi = "10.1109/ISCAS.2012.6271681",
language = "English",
isbn = "9781467302197",
publisher = "Institute of Electrical and Electronics Engineers",
pages = "2039--2042",
booktitle = "ISCAS 2012: 2012 IEEE International Symposium on Circuits and Systems, May 20-23, 2012, Seoul, Korea",
note = "IEEE International Symposium on Circuits and Systems ; Conference date: 20-05-2012",
}