A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Farhad Mehdipour; Hamid Noori; Bahman Javadi; Hiroaki Honda; Koji Inoue; Kazuaki Murakami

doi:10.1109/ASPDAC.2009.4796540

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami

School of Computer, Data & Mathematical Sciences

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

3 Citations (Scopus)

Abstract

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan
Publisher	IEEE
Pages	564-569
Number of pages	6
ISBN (Print)	9781424427499
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796540
Publication status	Published - 2009
Event	Asia and South Pacific Design Automation Conference - Duration: 19 Jan 2009 → …

Conference

Conference	Asia and South Pacific Design Automation Conference
Period	19/01/09 → …

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10.1109/ASPDAC.2009.4796540

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Mehdipour, F., Noori, H., Javadi, B., Honda, H., Inoue, K., & Murakami, K. (2009). A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. In Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan (pp. 564-569). IEEE. https://doi.org/10.1109/ASPDAC.2009.4796540

@inproceedings{054aabfac25e4085bd807971fa7c9446,

title = "A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor",

abstract = "Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.",

author = "Farhad Mehdipour and Hamid Noori and Bahman Javadi and Hiroaki Honda and Koji Inoue and Kazuaki Murakami",

year = "2009",

doi = "10.1109/ASPDAC.2009.4796540",

language = "English",

isbn = "9781424427499",

pages = "564--569",

booktitle = "Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan",

publisher = "IEEE",

note = "Asia and South Pacific Design Automation Conference ; Conference date: 19-01-2009",

}

Mehdipour, F, Noori, H, Javadi, B, Honda, H, Inoue, K & Murakami, K 2009, A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. in Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan. IEEE, pp. 564-569, Asia and South Pacific Design Automation Conference, 19/01/09. https://doi.org/10.1109/ASPDAC.2009.4796540

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. / Mehdipour, Farhad; Noori, Hamid; Javadi, Bahman et al.
Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan. IEEE, 2009. p. 564-569.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

T1 - A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

AU - Mehdipour, Farhad

AU - Noori, Hamid

AU - Javadi, Bahman

AU - Honda, Hiroaki

AU - Inoue, Koji

AU - Murakami, Kazuaki

PY - 2009

Y1 - 2009

N2 - Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

AB - Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

UR - http://handle.uws.edu.au:8081/1959.7/562312

U2 - 10.1109/ASPDAC.2009.4796540

DO - 10.1109/ASPDAC.2009.4796540

M3 - Conference Paper

SN - 9781424427499

SP - 564

EP - 569

BT - Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan

PB - IEEE

T2 - Asia and South Pacific Design Automation Conference

Y2 - 19 January 2009

ER -

Mehdipour F, Noori H, Javadi B, Honda H, Inoue K, Murakami K. A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. In Proceedings of the ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference, 19-22 January 2009, Yokohama, Japan. IEEE. 2009. p. 564-569 doi: 10.1109/ASPDAC.2009.4796540

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

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