A compact reconfigurable mixed-signal implementation of synaptic plasticity in spiking neurons

We present a compact mixed-signal implementation of synaptic plasticity for both Spike Timing Dependent Plasticity (STDP) and Spike Timing Dependent Delay Plasticity (STDDP). The proposed mixed-signal implementation consists of an aVLSI time window generator and a digital adaptor. The weight and delay values are stored in a digital memory, and the adaptor will send these values to the time window generator using a digital spike of which the duration is modulated according to these values. The analogue time window generator will then generate a time window, which is required for the implementation of STDP and STDDP. The digital adaptor will carry out the weight/delay adaption using this time window. The aVLSI time window generator is compact (50 μm2 in IBM 130nm process) and we use a time multiplexing approach to achieve up to 65536 (64k) virtual digital adaptors with one physical adaptor, consuming only a fraction of the hardware resource on a Virtex 6 FPGA. Since the digital adaptor has been implemented on an FPGA, it can be easily reconfigured for different adaptation algorithms, which leaves it open for future development. Our mixed-signal implementation is therefore practical for implementing the synaptic plasticity in large-scale spiking neural networks running in real time. We show circuit simulation results illustrating both weight and delay adaptation.