A robust and energy-efficient near-threshold SRAM cell utilizing ballistic carbon nanotube wrap-gate transistors

In recent years, carbon nanotube FETs with their astounding electrical properties have been in the spotlight of nanoelectronics designers. Therefore, they have introduced as a promising candidate for VLSI applications. The aim of this work is to represent a robust energy-efficient SRAM cell based on wrap-gate CNTFET transistors. The proposed SRAM cell has been designed in a particular way that mitigates the need to utilize complex bit-conditioning circuitries to precharge the bit-lines during operations. Moreover, the proposed design utilizes high-threshold voltage multi-tube CNTFET transistors which are biased in the near-threshold region to achieve a power-efficient and a reasonable data transfer speed rate operation. To benchmark the functionality of the proposed SRAM cell, performance parameters including power, delay, etc. have been evaluated through rigorous simulations. The simulation results demonstrate that the proposed SRAM consumes 14.59 pW and 1.25 nW static and dynamic powers respectively (@V_dd=0.5V). The proposed design has 180 mV and 340 mV read and write static noise margins respectively and no failure has observed up to 5000 times repetition in Monte Carlo simulations. Based on the simulation results, the proposed CNTFET-based SRAM cell has the potential to be exploited as the basic platform for modern high-performance large memory arrays.