TY - JOUR
T1 - An analogue neuromorphic co-processor that utilizes device mismatch for learning applications
AU - Thakur, Chetan Singh
AU - Wang, Runchun
AU - Hamilton, Tara Julia
AU - Etienne-Cummings, Ralph
AU - Tapson, Jonathan
AU - Van Schaik, André
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/4
Y1 - 2018/4
N2 - As the integrated circuit (IC) technology advances into smaller nanometre feature sizes, a fixed-error noise known as device mismatch is introduced owing to the dissimilarity between transistors, and this degrades the accuracy of analog circuits. In this paper, we present an analog co-processor that uses this fixed-pattern noise to its advantage to perform complex computation. This circuit is an extension of our previously published trainable analogue block (TAB) framework and uses multiple inputs that substantially increase functionality. We present measurement results of our two-input analogue co-processor built using a 130-nm process technology and show its learning capabilities for regression and classification tasks. We also show that the co-processor, comprised of 100 neurons, is a low-power system with a power dissipation of only 1.1μ W. The IC fabrication process contributes to randomness and variability in ICs, and we show that random device mismatch is favorable for the learning capability of our system as it causes variability among the neuronal tuning curves. The low-power capability of our framework makes it suitable for use in various battery-powered applications ranging from biomedical to military as a front-end analog co-processor.
AB - As the integrated circuit (IC) technology advances into smaller nanometre feature sizes, a fixed-error noise known as device mismatch is introduced owing to the dissimilarity between transistors, and this degrades the accuracy of analog circuits. In this paper, we present an analog co-processor that uses this fixed-pattern noise to its advantage to perform complex computation. This circuit is an extension of our previously published trainable analogue block (TAB) framework and uses multiple inputs that substantially increase functionality. We present measurement results of our two-input analogue co-processor built using a 130-nm process technology and show its learning capabilities for regression and classification tasks. We also show that the co-processor, comprised of 100 neurons, is a low-power system with a power dissipation of only 1.1μ W. The IC fabrication process contributes to randomness and variability in ICs, and we show that random device mismatch is favorable for the learning capability of our system as it causes variability among the neuronal tuning curves. The low-power capability of our framework makes it suitable for use in various battery-powered applications ranging from biomedical to military as a front-end analog co-processor.
KW - integrated circuits
KW - neural circuitry
KW - neuromorphic engineering
UR - http://handle.westernsydney.edu.au:8081/1959.7/uws:46422
U2 - 10.1109/TCSI.2017.2756878
DO - 10.1109/TCSI.2017.2756878
M3 - Article
SN - 1549-8328
VL - 65
SP - 1174
EP - 1184
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 4
ER -