An analogue VLSI implementation of polychronous spiking neural networks

Runchun Wang; Jonathan Tapson; Tara Julia Hamilton; André van Schaik

doi:10.1109/ISSNIP.2011.6146572

An analogue VLSI implementation of polychronous spiking neural networks

Runchun Wang, Jonathan Tapson, Tara Julia Hamilton, André van Schaik

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

9 Citations (Scopus)

Abstract

![CDATA[We present an analogue VLSI implementation of a polychronous network of spiking neurons. The network is capable of storing and retrieving spatial-temporal spike patterns. It consists of 14 leaky-integrate-and-fire neurons and corresponding axonal connections with programmable delays.]]

Original language	English
Title of host publication	Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), 6-9 December 2011, Adelaide, South Australia
Publisher	IEEE
Pages	97-102
Number of pages	6
ISBN (Print)	9781457706745
DOIs	https://doi.org/10.1109/ISSNIP.2011.6146572
Publication status	Published - 2011
Event	Intelligent Sensors_Sensor Networks & Information Processing Conference - Duration: 6 Dec 2011 → …

Conference

Conference	Intelligent Sensors_Sensor Networks & Information Processing Conference
Period	6/12/11 → …

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10.1109/ISSNIP.2011.6146572

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Wang, R., Tapson, J., Hamilton, T. J., & Schaik, A. V. (2011). An analogue VLSI implementation of polychronous spiking neural networks. In Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), 6-9 December 2011, Adelaide, South Australia (pp. 97-102). IEEE. https://doi.org/10.1109/ISSNIP.2011.6146572

@inproceedings{d8fd441304e84a9ebdf16d551af2ccfc,

title = "An analogue VLSI implementation of polychronous spiking neural networks",

abstract = "![CDATA[We present an analogue VLSI implementation of a polychronous network of spiking neurons. The network is capable of storing and retrieving spatial-temporal spike patterns. It consists of 14 leaky-integrate-and-fire neurons and corresponding axonal connections with programmable delays.]]",

author = "Runchun Wang and Jonathan Tapson and Hamilton, {Tara Julia} and Schaik, {Andr{\'e} van}",

year = "2011",

doi = "10.1109/ISSNIP.2011.6146572",

language = "English",

isbn = "9781457706745",

pages = "97--102",

booktitle = "Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), 6-9 December 2011, Adelaide, South Australia",

publisher = "IEEE",

note = "Intelligent Sensors_Sensor Networks & Information Processing Conference ; Conference date: 06-12-2011",

}

Wang, R, Tapson, J, Hamilton, TJ & Schaik, AV 2011, An analogue VLSI implementation of polychronous spiking neural networks. in Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), 6-9 December 2011, Adelaide, South Australia. IEEE, pp. 97-102, Intelligent Sensors_Sensor Networks & Information Processing Conference, 6/12/11. https://doi.org/10.1109/ISSNIP.2011.6146572

An analogue VLSI implementation of polychronous spiking neural networks. / Wang, Runchun; Tapson, Jonathan; Hamilton, Tara Julia et al.
Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), 6-9 December 2011, Adelaide, South Australia. IEEE, 2011. p. 97-102.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

T1 - An analogue VLSI implementation of polychronous spiking neural networks

AU - Wang, Runchun

AU - Tapson, Jonathan

AU - Hamilton, Tara Julia

AU - Schaik, André van

PY - 2011

Y1 - 2011

N2 - ![CDATA[We present an analogue VLSI implementation of a polychronous network of spiking neurons. The network is capable of storing and retrieving spatial-temporal spike patterns. It consists of 14 leaky-integrate-and-fire neurons and corresponding axonal connections with programmable delays.]]

AB - ![CDATA[We present an analogue VLSI implementation of a polychronous network of spiking neurons. The network is capable of storing and retrieving spatial-temporal spike patterns. It consists of 14 leaky-integrate-and-fire neurons and corresponding axonal connections with programmable delays.]]

UR - http://handle.uws.edu.au:8081/1959.7/543454

UR - http://www.issnip.org/2011/

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DO - 10.1109/ISSNIP.2011.6146572

M3 - Conference Paper

SN - 9781457706745

SP - 97

EP - 102

BT - Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), 6-9 December 2011, Adelaide, South Australia

PB - IEEE

T2 - Intelligent Sensors_Sensor Networks & Information Processing Conference

Y2 - 6 December 2011

ER -

An analogue VLSI implementation of polychronous spiking neural networks

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