An asynchronous parallel neuromorphic ADC architecture

Jonathan Tapson; André van Schaik

doi:10.1109/ISCAS.2012.6271783

An asynchronous parallel neuromorphic ADC architecture

Jonathan Tapson, André van Schaik

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

10 Citations (Scopus)

Abstract

![CDATA[A new parallel ADC architecture is presented which makes use of neuromorphic principles to be fast, accurate, and robust to noise and circuit mismatch. The architecture uses spiking integrate-and-fire neurons as base elements, with lateral inhibition to decohere the parallel pathways, and alternate on-and off-triggered paths to maintain a constant spike rate. Results from a proof-of-concept circuit reinforce the analytical conclusion that this circuit can make a practical ADC.]]

Original language	English
Title of host publication	2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea
Publisher	IEEE
Pages	2409-2412
Number of pages	4
ISBN (Print)	9781467302197
DOIs	https://doi.org/10.1109/ISCAS.2012.6271783
Publication status	Published - 2012
Event	IEEE International Symposium on Circuits and Systems - Duration: 20 May 2012 → …

Conference

Conference	IEEE International Symposium on Circuits and Systems
Period	20/05/12 → …

Keywords

ADC architectures
analog-to-digital converters
electric network analysis
neuromorphic
neurons

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10.1109/ISCAS.2012.6271783

Cite this

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title = "An asynchronous parallel neuromorphic ADC architecture",

abstract = "![CDATA[A new parallel ADC architecture is presented which makes use of neuromorphic principles to be fast, accurate, and robust to noise and circuit mismatch. The architecture uses spiking integrate-and-fire neurons as base elements, with lateral inhibition to decohere the parallel pathways, and alternate on-and off-triggered paths to maintain a constant spike rate. Results from a proof-of-concept circuit reinforce the analytical conclusion that this circuit can make a practical ADC.]]",

keywords = "ADC architectures, analog-to-digital converters, electric network analysis, neuromorphic, neurons",

author = "Jonathan Tapson and Schaik, {Andr{\'e} van}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271783",

language = "English",

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pages = "2409--2412",

booktitle = "2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea",

publisher = "IEEE",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 20-05-2012",

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TY - GEN

T1 - An asynchronous parallel neuromorphic ADC architecture

AU - Tapson, Jonathan

AU - Schaik, André van

PY - 2012

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N2 - ![CDATA[A new parallel ADC architecture is presented which makes use of neuromorphic principles to be fast, accurate, and robust to noise and circuit mismatch. The architecture uses spiking integrate-and-fire neurons as base elements, with lateral inhibition to decohere the parallel pathways, and alternate on-and off-triggered paths to maintain a constant spike rate. Results from a proof-of-concept circuit reinforce the analytical conclusion that this circuit can make a practical ADC.]]

AB - ![CDATA[A new parallel ADC architecture is presented which makes use of neuromorphic principles to be fast, accurate, and robust to noise and circuit mismatch. The architecture uses spiking integrate-and-fire neurons as base elements, with lateral inhibition to decohere the parallel pathways, and alternate on-and off-triggered paths to maintain a constant spike rate. Results from a proof-of-concept circuit reinforce the analytical conclusion that this circuit can make a practical ADC.]]

KW - ADC architectures

KW - analog-to-digital converters

KW - electric network analysis

KW - neuromorphic

KW - neurons

UR - http://handle.uws.edu.au:8081/1959.7/521288

UR - http://www.iscas2012.org/index.html

U2 - 10.1109/ISCAS.2012.6271783

DO - 10.1109/ISCAS.2012.6271783

M3 - Conference Paper

SN - 9781467302197

SP - 2409

EP - 2412

BT - 2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 20 May 2012

ER -

An asynchronous parallel neuromorphic ADC architecture

Abstract

Conference

Keywords

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