An asynchronous viterbi decoder for low-power applications

B. Javadi; M. Naderi; H. Pedram; A. Afzali-Kusha; M. K. Akbari

doi:10.1007/978-3-540-39762-5_53

An asynchronous viterbi decoder for low-power applications

B. Javadi, M. Naderi, H. Pedram, A. Afzali-Kusha, M. K. Akbari

Research output: Chapter in Book / Conference Paper › Chapter › peer-review

4 Citations (Scopus)

Abstract

This paper presents a robust and low-power Viterbi Decoder designed based on asynchronous architecture. The design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust functionality for the decoder. To lower the power consumption of the decoder further, an optimization technique to reduce the power dissipation is applied to add-compare-select (ACS) unit of the decoder. The simulation results shows a 20% reduction in the power consumption for the asynchronous design compared to the synchronous design in 0.35μm CMOS technology with a power supply of 2.5V. The throughput for the circuit is 50 MS/s.

Original language	English
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Editors	Jorge Juan Chico, Enrico Macii
Publisher	Springer Verlag
Pages	471-480
Number of pages	10
ISBN (Electronic)	3540200746, 9783540200741
DOIs	https://doi.org/10.1007/978-3-540-39762-5_53
Publication status	Published - 2003
Externally published	Yes

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	2799
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

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10.1007/978-3-540-39762-5_53

Cite this

Javadi, B., Naderi, M., Pedram, H., Afzali-Kusha, A., & Akbari, M. K. (2003). An asynchronous viterbi decoder for low-power applications. In J. J. Chico, & E. Macii (Eds.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 471-480). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2799). Springer Verlag. https://doi.org/10.1007/978-3-540-39762-5_53

Javadi, B. ; Naderi, M. ; Pedram, H. et al. / An asynchronous viterbi decoder for low-power applications. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). editor / Jorge Juan Chico ; Enrico Macii. Springer Verlag, 2003. pp. 471-480 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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author = "B. Javadi and M. Naderi and H. Pedram and A. Afzali-Kusha and Akbari, {M. K.}",

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Javadi, B, Naderi, M, Pedram, H, Afzali-Kusha, A & Akbari, MK 2003, An asynchronous viterbi decoder for low-power applications. in JJ Chico & E Macii (eds), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2799, Springer Verlag, pp. 471-480. https://doi.org/10.1007/978-3-540-39762-5_53

An asynchronous viterbi decoder for low-power applications. / Javadi, B.; Naderi, M.; Pedram, H. et al.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). ed. / Jorge Juan Chico; Enrico Macii. Springer Verlag, 2003. p. 471-480 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2799).

Research output: Chapter in Book / Conference Paper › Chapter › peer-review

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AB - This paper presents a robust and low-power Viterbi Decoder designed based on asynchronous architecture. The design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust functionality for the decoder. To lower the power consumption of the decoder further, an optimization technique to reduce the power dissipation is applied to add-compare-select (ACS) unit of the decoder. The simulation results shows a 20% reduction in the power consumption for the asynchronous design compared to the synchronous design in 0.35μm CMOS technology with a power supply of 2.5V. The throughput for the circuit is 50 MS/s.

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Javadi B, Naderi M, Pedram H, Afzali-Kusha A, Akbari MK. An asynchronous viterbi decoder for low-power applications. In Chico JJ, Macii E, editors, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag. 2003. p. 471-480. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-39762-5_53

An asynchronous viterbi decoder for low-power applications

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