An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation

Runchun Wang; Jonathan Tapson; Tara Julia Hamilton; André van Schaik

doi:10.1109/ISCAS.2012.6271785

An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation

Runchun Wang, Jonathan Tapson, Tara Julia Hamilton, André van Schaik

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

9 Citations (Scopus)

Abstract

![CDATA[We present measurements from an aVLSI programmable axonal propagation delay circuit. It is intended to be used in the implementation of polychronous spiking neural networks. The delay can be programmed by presenting an input spike followed by a training spike at the desired delay. To fine tune and maintain the delay using an analogue memory, we use continuous spike timing dependent delay adaptation. Measurements presented here show that the axon circuit is capable of learning and retaining delays in the 2.5-20 ms range, as long as the neuron is stimulated at least once every few seconds.]]

Original language	English
Title of host publication	2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea
Publisher	IEEE
Pages	2413-2416
Number of pages	4
ISBN (Print)	9781467302197
DOIs	https://doi.org/10.1109/ISCAS.2012.6271785
Publication status	Published - 2012
Event	IEEE International Symposium on Circuits and Systems - Duration: 20 May 2012 → …

Conference

Conference	IEEE International Symposium on Circuits and Systems
Period	20/05/12 → …

Keywords

analogue VLSI
axonal propogation delays
delay adaptation
neural networks (computer science)
spiking neurons

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10.1109/ISCAS.2012.6271785

Cite this

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title = "An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation",

abstract = "![CDATA[We present measurements from an aVLSI programmable axonal propagation delay circuit. It is intended to be used in the implementation of polychronous spiking neural networks. The delay can be programmed by presenting an input spike followed by a training spike at the desired delay. To fine tune and maintain the delay using an analogue memory, we use continuous spike timing dependent delay adaptation. Measurements presented here show that the axon circuit is capable of learning and retaining delays in the 2.5-20 ms range, as long as the neuron is stimulated at least once every few seconds.]]",

keywords = "analogue VLSI, axonal propogation delays, delay adaptation, neural networks (computer science), spiking neurons",

author = "Runchun Wang and Jonathan Tapson and Hamilton, {Tara Julia} and Schaik, {Andr{\'e} van}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271785",

language = "English",

isbn = "9781467302197",

pages = "2413--2416",

booktitle = "2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea",

publisher = "IEEE",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 20-05-2012",

}

Wang, R, Tapson, J, Hamilton, TJ & Schaik, AV 2012, An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation. in 2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea. IEEE, pp. 2413-2416, IEEE International Symposium on Circuits and Systems, 20/05/12. https://doi.org/10.1109/ISCAS.2012.6271785

TY - GEN

T1 - An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation

AU - Wang, Runchun

AU - Tapson, Jonathan

AU - Hamilton, Tara Julia

AU - Schaik, André van

PY - 2012

Y1 - 2012

N2 - ![CDATA[We present measurements from an aVLSI programmable axonal propagation delay circuit. It is intended to be used in the implementation of polychronous spiking neural networks. The delay can be programmed by presenting an input spike followed by a training spike at the desired delay. To fine tune and maintain the delay using an analogue memory, we use continuous spike timing dependent delay adaptation. Measurements presented here show that the axon circuit is capable of learning and retaining delays in the 2.5-20 ms range, as long as the neuron is stimulated at least once every few seconds.]]

AB - ![CDATA[We present measurements from an aVLSI programmable axonal propagation delay circuit. It is intended to be used in the implementation of polychronous spiking neural networks. The delay can be programmed by presenting an input spike followed by a training spike at the desired delay. To fine tune and maintain the delay using an analogue memory, we use continuous spike timing dependent delay adaptation. Measurements presented here show that the axon circuit is capable of learning and retaining delays in the 2.5-20 ms range, as long as the neuron is stimulated at least once every few seconds.]]

KW - analogue VLSI

KW - axonal propogation delays

KW - delay adaptation

KW - neural networks (computer science)

KW - spiking neurons

UR - http://handle.uws.edu.au:8081/1959.7/521284

UR - http://www.iscas2012.org/index.html

U2 - 10.1109/ISCAS.2012.6271785

DO - 10.1109/ISCAS.2012.6271785

M3 - Conference Paper

SN - 9781467302197

SP - 2413

EP - 2416

BT - 2012 IEEE International Symposium on Circuits and Systems: ISCAS 2012: 20-23 May 2012, Seoul, Korea

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 20 May 2012

ER -

An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation

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