An FPGA implementation of an event-driven unsupervised feature extraction algorithm for pattern recognition

Philip C. Jose; Ying Xu; André Van Schaik; Runchun Wang

doi:10.1109/ISCAS58744.2024.10558113

An FPGA implementation of an event-driven unsupervised feature extraction algorithm for pattern recognition

Philip C. Jose, Ying Xu, André Van Schaik, Runchun Wang

Western Sydney University

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

2 Citations (Scopus)

Abstract

This paper presents the Field Programmable Gate Array (FPGA) implementation of an event-driven unsupervised Feature Extraction using Adaptive Selection Thresholds (FEAST) algorithm for pattern recognition tasks. The novelty of the design lies in splitting the FEAST learning rule into two different sets of tasks and executing them independently in a time-multiplexed fashion, using a minimum number of hardware resources. The proposed hardware architecture, operated at 200 MHz clock frequency, can process 183 Ã— 103 events/sec in training mode and 196Ã—103 events/sec in inference mode. The FEAST hardware model was tested with the Poker DVS dataset, obtaining a test accuracy of 95%.

Original language	English
Title of host publication	ISCAS 2024: IEEE International Symposium on Circuits and Systems, May 19-22, 2024, Singapore
Place of Publication	U.S.
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	9798350330991
DOIs	https://doi.org/10.1109/ISCAS58744.2024.10558113
Publication status	Published - 2024
Event	2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore Duration: 19 May 2024 → 22 May 2024

Conference

Conference	2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Country/Territory	Singapore
City	Singapore
Period	19/05/24 → 22/05/24

Keywords

event-based feature extraction
FPGA
neuromorphic engineering
time surface

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10.1109/ISCAS58744.2024.10558113

Cite this

@inproceedings{81aac0973dcf49e4853b53d3f2db5ed8,

title = "An FPGA implementation of an event-driven unsupervised feature extraction algorithm for pattern recognition",

abstract = "This paper presents the Field Programmable Gate Array (FPGA) implementation of an event-driven unsupervised Feature Extraction using Adaptive Selection Thresholds (FEAST) algorithm for pattern recognition tasks. The novelty of the design lies in splitting the FEAST learning rule into two different sets of tasks and executing them independently in a time-multiplexed fashion, using a minimum number of hardware resources. The proposed hardware architecture, operated at 200 MHz clock frequency, can process 183 {\~A}— 103 events/sec in training mode and 196{\~A}—103 events/sec in inference mode. The FEAST hardware model was tested with the Poker DVS dataset, obtaining a test accuracy of 95%.",

keywords = "event-based feature extraction, FPGA, neuromorphic engineering, time surface",

author = "Jose, {Philip C.} and Ying Xu and {Van Schaik}, Andr{\'e} and Runchun Wang",

year = "2024",

doi = "10.1109/ISCAS58744.2024.10558113",

language = "English",

booktitle = "ISCAS 2024: IEEE International Symposium on Circuits and Systems, May 19-22, 2024, Singapore",

publisher = "IEEE",

note = "2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",

}

Jose, PC, Xu, Y , Van Schaik, A & Wang, R 2024, An FPGA implementation of an event-driven unsupervised feature extraction algorithm for pattern recognition. in ISCAS 2024: IEEE International Symposium on Circuits and Systems, May 19-22, 2024, Singapore. IEEE, U.S., 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, Singapore, 19/05/24. https://doi.org/10.1109/ISCAS58744.2024.10558113

TY - GEN

T1 - An FPGA implementation of an event-driven unsupervised feature extraction algorithm for pattern recognition

AU - Jose, Philip C.

AU - Xu, Ying

AU - Van Schaik, André

AU - Wang, Runchun

PY - 2024

Y1 - 2024

N2 - This paper presents the Field Programmable Gate Array (FPGA) implementation of an event-driven unsupervised Feature Extraction using Adaptive Selection Thresholds (FEAST) algorithm for pattern recognition tasks. The novelty of the design lies in splitting the FEAST learning rule into two different sets of tasks and executing them independently in a time-multiplexed fashion, using a minimum number of hardware resources. The proposed hardware architecture, operated at 200 MHz clock frequency, can process 183 Ã— 103 events/sec in training mode and 196Ã—103 events/sec in inference mode. The FEAST hardware model was tested with the Poker DVS dataset, obtaining a test accuracy of 95%.

AB - This paper presents the Field Programmable Gate Array (FPGA) implementation of an event-driven unsupervised Feature Extraction using Adaptive Selection Thresholds (FEAST) algorithm for pattern recognition tasks. The novelty of the design lies in splitting the FEAST learning rule into two different sets of tasks and executing them independently in a time-multiplexed fashion, using a minimum number of hardware resources. The proposed hardware architecture, operated at 200 MHz clock frequency, can process 183 Ã— 103 events/sec in training mode and 196Ã—103 events/sec in inference mode. The FEAST hardware model was tested with the Poker DVS dataset, obtaining a test accuracy of 95%.

KW - event-based feature extraction

KW - FPGA

KW - neuromorphic engineering

KW - time surface

UR - http://www.scopus.com/inward/record.url?scp=85198540696&partnerID=8YFLogxK

UR - https://go.openathens.net/redirector/westernsydney.edu.au?url=https://doi.org/10.1109/ISCAS58744.2024.10558113

U2 - 10.1109/ISCAS58744.2024.10558113

DO - 10.1109/ISCAS58744.2024.10558113

M3 - Conference Paper

AN - SCOPUS:85198540696

BT - ISCAS 2024: IEEE International Symposium on Circuits and Systems, May 19-22, 2024, Singapore

PB - IEEE

CY - U.S.

T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024

Y2 - 19 May 2024 through 22 May 2024

ER -

An FPGA implementation of an event-driven unsupervised feature extraction algorithm for pattern recognition

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Keywords

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