An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity

Runchun Wang; Gregory Cohen; Tara Hamilton; Jonathan Tapson; André van Schaik

doi:10.1109/ISCAS.2013.6572165

An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity

Runchun Wang, Gregory Cohen, Tara Hamilton, Jonathan Tapson, André van Schaik

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

6 Citations (Scopus)

Abstract

We present a voltage domain implementation of a programmable delay axon circuit together with measurements from it. It was designed to be a building block for a polychronous spiking neural network. The axonal delay can be programmed by presenting an input spike followed by a post-synaptic spike at the desired delay. An analogue memory was used to store this value. We also use spike timing dependent delay plasticity (STDDP) to reduce the errors in delay that result from the delay programming step. Measurements show that the proposed circuit is capable of learning and retaining delays in the range of 2 ms to 50 ms for many minutes.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China
Publisher	IEEE Xplore
Pages	1592-1595
Number of pages	4
ISBN (Print)	9781467357609
DOIs	https://doi.org/10.1109/ISCAS.2013.6572165
Publication status	Published - 2013
Event	IEEE International Symposium on Circuits and Systems - Duration: 19 May 2013 → …

Publication series

Name
ISSN (Print)	0271-4302

Conference

Conference	IEEE International Symposium on Circuits and Systems
Period	19/05/13 → …

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10.1109/ISCAS.2013.6572165

Cite this

@inproceedings{4c6661b0b0b540dabbef84cb66ffd8af,

title = "An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity",

abstract = "We present a voltage domain implementation of a programmable delay axon circuit together with measurements from it. It was designed to be a building block for a polychronous spiking neural network. The axonal delay can be programmed by presenting an input spike followed by a post-synaptic spike at the desired delay. An analogue memory was used to store this value. We also use spike timing dependent delay plasticity (STDDP) to reduce the errors in delay that result from the delay programming step. Measurements show that the proposed circuit is capable of learning and retaining delays in the range of 2 ms to 50 ms for many minutes.",

author = "Runchun Wang and Gregory Cohen and Tara Hamilton and Jonathan Tapson and Schaik, {Andr{\'e} van}",

year = "2013",

doi = "10.1109/ISCAS.2013.6572165",

language = "English",

isbn = "9781467357609",

publisher = "IEEE Xplore",

pages = "1592--1595",

booktitle = "Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 19-05-2013",

}

Wang, R , Cohen, G, Hamilton, T, Tapson, J & Schaik, AV 2013, An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity. in Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China. IEEE Xplore, pp. 1592-1595, IEEE International Symposium on Circuits and Systems, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6572165

An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity. / Wang, Runchun ; Cohen, Gregory; Hamilton, Tara et al.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China. IEEE Xplore, 2013. p. 1592-1595.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

T1 - An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity

AU - Wang, Runchun

AU - Cohen, Gregory

AU - Hamilton, Tara

AU - Tapson, Jonathan

AU - Schaik, André van

PY - 2013

Y1 - 2013

N2 - We present a voltage domain implementation of a programmable delay axon circuit together with measurements from it. It was designed to be a building block for a polychronous spiking neural network. The axonal delay can be programmed by presenting an input spike followed by a post-synaptic spike at the desired delay. An analogue memory was used to store this value. We also use spike timing dependent delay plasticity (STDDP) to reduce the errors in delay that result from the delay programming step. Measurements show that the proposed circuit is capable of learning and retaining delays in the range of 2 ms to 50 ms for many minutes.

AB - We present a voltage domain implementation of a programmable delay axon circuit together with measurements from it. It was designed to be a building block for a polychronous spiking neural network. The axonal delay can be programmed by presenting an input spike followed by a post-synaptic spike at the desired delay. An analogue memory was used to store this value. We also use spike timing dependent delay plasticity (STDDP) to reduce the errors in delay that result from the delay programming step. Measurements show that the proposed circuit is capable of learning and retaining delays in the range of 2 ms to 50 ms for many minutes.

UR - http://handle.uws.edu.au:8081/1959.7/532986

UR - http://iscas2013.org/

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DO - 10.1109/ISCAS.2013.6572165

M3 - Conference Paper

SN - 9781467357609

SP - 1592

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BT - Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, 19-23 May 2013, Beijing, China

PB - IEEE Xplore

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 19 May 2013

ER -

An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity

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