An RNS based modular multiplier with reduced complexity

Shahzad Asif; Mark Vesterbacka

doi:10.1109/NORCHIP.2017.8124953

An RNS based modular multiplier with reduced complexity

Shahzad Asif, Mark Vesterbacka

Western Sydney University

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

Abstract

Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

Original language	English
Title of host publication	2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 24 - 25 October, 2017, Linkoping, Sweden, Conference Proceedings
Publisher	IEEE
Number of pages	4
ISBN (Print)	9781538628447
DOIs	https://doi.org/10.1109/NORCHIP.2017.8124953
Publication status	Published - 2017
Event	IEEE Nordic Circuits and Systems Conference - Duration: 24 Oct 2017 → …

Conference

Conference	IEEE Nordic Circuits and Systems Conference
Period	24/10/17 → …

Keywords

modules (algebra)

Access to Document

10.1109/NORCHIP.2017.8124953

Cite this

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title = "An RNS based modular multiplier with reduced complexity",

abstract = "Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.",

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author = "Shahzad Asif and Mark Vesterbacka",

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booktitle = "2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 24 - 25 October, 2017, Linkoping, Sweden, Conference Proceedings",

publisher = "IEEE",

note = "IEEE Nordic Circuits and Systems Conference ; Conference date: 24-10-2017",

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Asif, S & Vesterbacka, M 2017, An RNS based modular multiplier with reduced complexity. in 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 24 - 25 October, 2017, Linkoping, Sweden, Conference Proceedings. IEEE, IEEE Nordic Circuits and Systems Conference, 24/10/17. https://doi.org/10.1109/NORCHIP.2017.8124953

An RNS based modular multiplier with reduced complexity. / Asif, Shahzad; Vesterbacka, Mark.
2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 24 - 25 October, 2017, Linkoping, Sweden, Conference Proceedings. IEEE, 2017.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

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AU - Asif, Shahzad

AU - Vesterbacka, Mark

PY - 2017

Y1 - 2017

N2 - Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

AB - Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

KW - modules (algebra)

UR - http://handle.westernsydney.edu.au:8081/1959.7/uws:46416

U2 - 10.1109/NORCHIP.2017.8124953

DO - 10.1109/NORCHIP.2017.8124953

M3 - Conference Paper

SN - 9781538628447

BT - 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 24 - 25 October, 2017, Linkoping, Sweden, Conference Proceedings

PB - IEEE

T2 - IEEE Nordic Circuits and Systems Conference

Y2 - 24 October 2017

ER -

An RNS based modular multiplier with reduced complexity

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