An SRAM-based implementation of a convolutional neural network

In the last decade, computational neuroscience and machine learning communities have witnessed the emergence of several algorithms where an input signal is randomly projected to a higher dimensional space via a nonlinear activation function. These methods are increasingly popular for regression or classification tasks, but this kind of neural network has remained difficult to implement efficiently in hardware. This is partly due to the all-to-all connectivity required between the input and hidden layers in these networks. The concept of using receptive fields (RF) for classification tasks stems from biology, in which sensory neurons often respond to a limited spatial range of the input stimulus. Incorporating this methodology into a classification system often yields an increase in performance. This paper presents an SRAM-based implementation of the RF approach to implement this kind of neural network on hardware. Since SRAM has a much smaller footprint compared to logic gates, this implementation is much more efficient in terms of hardware resources. The system was implemented and verified on an FPGA to demonstrate the efficiencies and flexibility of this approach for MNIST digit recognition task.