Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

Astria Nur Irfansyah; Torsten Lehmann; Julian Jenkins; Tara Julia Hamilton

doi:10.1109/TENCONSpring.2013.6584427

Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

Astria Nur Irfansyah, Torsten Lehmann, Julian Jenkins, Tara Julia Hamilton

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

6 Citations (Scopus)

Abstract

This paper deals with the design aspect of current-steering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic non-linearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-Î¼m CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.

Original language	English
Title of host publication	IEEE 2013 Tencon-Spring: April 17th - 19th, 2013, Sydney, Australia: Conference Proceedings
Publisher	IEEE
Pages	108-111
Number of pages	4
ISBN (Print)	9781467363495
DOIs	https://doi.org/10.1109/TENCONSpring.2013.6584427
Publication status	Published - 2013
Event	TENCON-Spring - Duration: 17 Apr 2013 → …

Conference

Conference	TENCON-Spring
Period	17/04/13 → …

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10.1109/TENCONSpring.2013.6584427

Cite this

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title = "Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC",

abstract = "This paper deals with the design aspect of current-steering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic non-linearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-{\^I}¼m CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.",

author = "Irfansyah, {Astria Nur} and Torsten Lehmann and Julian Jenkins and Hamilton, {Tara Julia}",

year = "2013",

doi = "10.1109/TENCONSpring.2013.6584427",

language = "English",

isbn = "9781467363495",

pages = "108--111",

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note = "TENCON-Spring ; Conference date: 17-04-2013",

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Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC. / Irfansyah, Astria Nur; Lehmann, Torsten; Jenkins, Julian et al.
IEEE 2013 Tencon-Spring: April 17th - 19th, 2013, Sydney, Australia: Conference Proceedings. IEEE, 2013. p. 108-111.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

T1 - Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

AU - Irfansyah, Astria Nur

AU - Lehmann, Torsten

AU - Jenkins, Julian

AU - Hamilton, Tara Julia

PY - 2013

Y1 - 2013

N2 - This paper deals with the design aspect of current-steering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic non-linearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-Î¼m CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.

AB - This paper deals with the design aspect of current-steering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic non-linearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-Î¼m CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.

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DO - 10.1109/TENCONSpring.2013.6584427

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BT - IEEE 2013 Tencon-Spring: April 17th - 19th, 2013, Sydney, Australia: Conference Proceedings

PB - IEEE

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Y2 - 17 April 2013

ER -

Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

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