Area efficient, low power and robust design for Add-Compare-Select units

Mohammad K. Akbari; Ali Jahanian; Mohsen Naderi; Bahman Javadi

doi:10.1109/DSD.2004.1333334

Area efficient, low power and robust design for Add-Compare-Select units

Mohammad K. Akbari
, Ali Jahanian
, Mohsen Naderi
, Bahman Javadi

Amirkabir University of Technology

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

6 Citations (Scopus)

Abstract

This paper presents an area efficient, low-power and robust ACS unit for Viterbi Decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-Pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.

Original language	English
Title of host publication	Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
Editors	H. Selvaraj
Pages	611-614
Number of pages	4
DOIs	https://doi.org/10.1109/DSD.2004.1333334
Publication status	Published - 2004
Externally published	Yes
Event	Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004 - Rennes, France Duration: 31 Aug 2004 → 3 Sept 2004

Publication series

Name	Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Conference

Conference	Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
Country/Territory	France
City	Rennes
Period	31/08/04 → 3/09/04

Access to Document

10.1109/DSD.2004.1333334

Cite this

@inproceedings{87962e76385a439d810f62f27b77ca81,

title = "Area efficient, low power and robust design for Add-Compare-Select units",

abstract = "This paper presents an area efficient, low-power and robust ACS unit for Viterbi Decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-Pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.",

author = "Akbari, \{Mohammad K.\} and Ali Jahanian and Mohsen Naderi and Bahman Javadi",

year = "2004",

doi = "10.1109/DSD.2004.1333334",

language = "English",

isbn = "0769522033",

series = "Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004",

pages = "611--614",

editor = "H. Selvaraj",

booktitle = "Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004",

note = "Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004 ; Conference date: 31-08-2004 Through 03-09-2004",

}

Akbari, MK, Jahanian, A, Naderi, M & Javadi, B 2004, Area efficient, low power and robust design for Add-Compare-Select units. in H Selvaraj (ed.), Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004. Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004, pp. 611-614, Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004, Rennes, France, 31/08/04. https://doi.org/10.1109/DSD.2004.1333334

Area efficient, low power and robust design for Add-Compare-Select units. / Akbari, Mohammad K.; Jahanian, Ali; Naderi, Mohsen et al.
Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004. ed. / H. Selvaraj. 2004. p. 611-614 (Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004).

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

T1 - Area efficient, low power and robust design for Add-Compare-Select units

AU - Akbari, Mohammad K.

AU - Jahanian, Ali

AU - Naderi, Mohsen

AU - Javadi, Bahman

PY - 2004

Y1 - 2004

N2 - This paper presents an area efficient, low-power and robust ACS unit for Viterbi Decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-Pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.

AB - This paper presents an area efficient, low-power and robust ACS unit for Viterbi Decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-Pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.

UR - https://www.scopus.com/pages/publications/13944265015

U2 - 10.1109/DSD.2004.1333334

DO - 10.1109/DSD.2004.1333334

M3 - Conference Paper

AN - SCOPUS:13944265015

SN - 0769522033

SN - 9780769522036

T3 - Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

SP - 611

EP - 614

BT - Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

A2 - Selvaraj, H.

T2 - Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Y2 - 31 August 2004 through 3 September 2004

ER -

Area efficient, low power and robust design for Add-Compare-Select units

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