Abstract
This paper describes CMOS circuits that generate a wide-ranging set of fixed bias currents, spanning at least 6 decades down to picoamperes. A master current generated by a bootstrapped current reference is successively divided by a current splitter to generate the desired references. An unpublished startup circuit and a novel power control mechanism are described. Measurements from a 0.35u implementation are presented and non-idealities are investigated. Readers are directed to a design kit that makes it simple to generate the layout for a bias generator with a set of desired currents for scalable MOSIS CMOS processes.
| Original language | English |
|---|---|
| Pages (from-to) | I337-I340 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | 2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004 |