Abstract
In this paper we examine a digitally controllable Nauta structure implemented in a 65nm process and identify a strategy useful for calibrating the structure in such a way that a maximum gain is achieved. We propose an efficient and simple tuning procedure that could be the basis for an integrated on-chip calibration solution and investigate the feasibility of implementing it. The procedure would primarily rely on a digitally implemented control circuit to minimize the need for analogue circuitry and therefore area requirements, and power consumption.
| Original language | English |
|---|---|
| Title of host publication | APCCAS 2014: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), November 17–20, 2014, Ishigaki Island, Okinawa, Japan |
| Publisher | IEEE |
| Pages | 189-192 |
| Number of pages | 4 |
| ISBN (Print) | 9781479952304 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | IEEE Asia-Pacific Conference on Circuits and Systems - Duration: 17 Nov 2014 → … |
Conference
| Conference | IEEE Asia-Pacific Conference on Circuits and Systems |
|---|---|
| Period | 17/11/14 → … |
Keywords
- calibration
- metal oxide semiconductors, complementary
- operational amplifiers
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