Deep ICP-RIE etched trenches with sidewall slope control of GaAs-based high power 905nm pulsed laser diodes

The micro-fabrication process for advanced GaAs-based Pulsed Laser Diodes (PLDs) necessitates the precise etching of trenches for patterning waveguides. Traditionally, we employed wet etching in our approach, which, unfortunately, does not allow for precise engineering of waveguide trench geometry. The isotropic nature of wet etching results in a sidewall angle of approximately 45°. To enhance device performance, achieving a steeper angle without compromising other process steps dry etching is preferable. Ideally, trenches with sidewall angles ranging from 60-70° would strike an optimal balance. In pursuit of this goal, we initiated a Design of Experiment (DoE) to optimize the etching by Inductively Coupled Plasma - Reactive Ion Etching (ICP-RIE). Through this experimentation, we identified an ICP-RIE recipe capable of producing trenches with sidewall angles within the desired range (60°-70°), exhibiting low roughness and attaining a depth of 17 µm. After this optimization, we applied the new ICP-RIE process to fabricate PLDs and conducted a comparative analysis against devices produced using our conventional wet etching method. The PLDs etched with ICP-RIE showcased slightly superior performance compared to those etched with wet etching. The implementation of ICP-RIE not only enhances device performance but also allows for a reduction in footprint per device. Consequently, this optimization contributes to an increased yield of devices per wafer, thus demonstrating the potential for scalability and improved efficiency in our micro-fabrication process.