TY - GEN
T1 - Live demonstration
T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
AU - Krishna, Adithya
AU - Rajesh, Ashwin
AU - Oleti, Hitesh Pavan
AU - Chauhan, Anand
AU - H., Shankaranarayanan
AU - Van Schaik, André
AU - Mehendale, Mahesh
AU - Thakur, Chetan Singh
PY - 2024
Y1 - 2024
N2 - The setup includes a host PC, camera and microphone sensors, and a Pynq-Z2 FPGA board. The neuromorphic cochlear model and RAMAN accelerator for neural network inference are deployed on the FPGA. The ARM processor on the FPGA sends the image received, cochleagram and the classified outputs to the PC to be visualized.
AB - The setup includes a host PC, camera and microphone sensors, and a Pynq-Z2 FPGA board. The neuromorphic cochlear model and RAMAN accelerator for neural network inference are deployed on the FPGA. The ARM processor on the FPGA sends the image received, cochleagram and the classified outputs to the PC to be visualized.
UR - http://www.scopus.com/inward/record.url?scp=85198510995&partnerID=8YFLogxK
UR - https://ezproxy.uws.edu.au/login?url=https://doi.org/10.1109/ISCAS58744.2024.10558468
U2 - 10.1109/ISCAS58744.2024.10558468
DO - 10.1109/ISCAS58744.2024.10558468
M3 - Conference Paper
AN - SCOPUS:85198510995
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2024: IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
CY - U.S.
Y2 - 19 May 2024 through 22 May 2024
ER -