Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies

Ganesh Cheduluri; Swati Bhardwaj; Ganesh R. Naik; Vidhumouli Hansigida; Appa Rao Nali; Amit Acharyya

doi:10.1109/NEWCAS52662.2022.9842110

Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies

Ganesh Cheduluri, Swati Bhardwaj, Ganesh R. Naik, Vidhumouli Hansigida, Appa Rao Nali, Amit Acharyya

Western Sydney University

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

4 Citations (Scopus)

Abstract

The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure.

Original language	English
Title of host publication	NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022
Publisher	IEEE
Pages	70-74
Number of pages	5
ISBN (Print)	9781665401050
DOIs	https://doi.org/10.1109/NEWCAS52662.2022.9842110
Publication status	Published - 2022
Event	IEEE International New Circuits and Systems Conference - Duration: 19 Jun 2022 → …

Conference

Conference	IEEE International New Circuits and Systems Conference
Period	19/06/22 → …

Access to Document

10.1109/NEWCAS52662.2022.9842110

Cite this

Cheduluri, G., Bhardwaj, S., Naik, G. R., Hansigida, V., Nali, A. R., & Acharyya, A. (2022). Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies. In NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022 (pp. 70-74). IEEE. https://doi.org/10.1109/NEWCAS52662.2022.9842110

@inproceedings{36fe5153e2e443d1a9836a002ca4b189,

title = "Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies",

abstract = "The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure.",

author = "Ganesh Cheduluri and Swati Bhardwaj and Naik, {Ganesh R.} and Vidhumouli Hansigida and Nali, {Appa Rao} and Amit Acharyya",

year = "2022",

doi = "10.1109/NEWCAS52662.2022.9842110",

language = "English",

isbn = "9781665401050",

pages = "70--74",

booktitle = "NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022",

publisher = "IEEE",

note = "IEEE International New Circuits and Systems Conference ; Conference date: 19-06-2022",

}

Cheduluri, G, Bhardwaj, S, Naik, GR, Hansigida, V, Nali, AR & Acharyya, A 2022, Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies. in NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022. IEEE, pp. 70-74, IEEE International New Circuits and Systems Conference, 19/06/22. https://doi.org/10.1109/NEWCAS52662.2022.9842110

Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies. / Cheduluri, Ganesh; Bhardwaj, Swati; Naik, Ganesh R. et al.
NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022. IEEE, 2022. p. 70-74.

Research output: Chapter in Book / Conference Paper › Conference Paper › peer-review

TY - GEN

T1 - Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies

AU - Cheduluri, Ganesh

AU - Bhardwaj, Swati

AU - Naik, Ganesh R.

AU - Hansigida, Vidhumouli

AU - Nali, Appa Rao

AU - Acharyya, Amit

PY - 2022

Y1 - 2022

N2 - The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure.

AB - The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure.

UR - https://hdl.handle.net/1959.7/uws:75498

U2 - 10.1109/NEWCAS52662.2022.9842110

DO - 10.1109/NEWCAS52662.2022.9842110

M3 - Conference Paper

SN - 9781665401050

SP - 70

EP - 74

BT - NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022

PB - IEEE

T2 - IEEE International New Circuits and Systems Conference

Y2 - 19 June 2022

ER -

Cheduluri G, Bhardwaj S, Naik GR, Hansigida V, Nali AR, Acharyya A. Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies. In NEWCAS 2022: Proceedings of the 20th IEEE International New Circuits and Systems Conference, Quebec City, June 19-22, 2022. IEEE. 2022. p. 70-74 doi: 10.1109/NEWCAS52662.2022.9842110

Low complex hardware architecture design methodology for cubic spline interpolation technique for assistive technologies

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this