Low power, CMOS-MoS2 memtransistor based neuromorphic hybrid architecture for wake-up systems

Sarthak Gupta; Pratik Kumar; Tathagata Paul; Andre van Schaik; Arindam Ghosh; Chetan Singh Thakur

doi:10.1038/s41598-019-51606-x

Low power, CMOS-MoS2 memtransistor based neuromorphic hybrid architecture for wake-up systems

Sarthak Gupta, Pratik Kumar, Tathagata Paul, Andre van Schaik, Arindam Ghosh, Chetan Singh Thakur

Western Sydney University

Research output: Contribution to journal › Article › peer-review

27 Citations (Scopus)

Abstract

Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

Original language	English
Article number	15604
Number of pages	9
Journal	Scientific Reports
Volume	9
Issue number	1
DOIs	https://doi.org/10.1038/s41598-019-51606-x
Publication status	Published - 2019

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Keywords

analog CMOS integrated circuits
computer network architectures
low voltage integrated circuits
neuromorphics

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10.1038/s41598-019-51606-x

Cite this

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title = "Low power, CMOS-MoS2 memtransistor based neuromorphic hybrid architecture for wake-up systems",

abstract = "Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.",

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author = "Sarthak Gupta and Pratik Kumar and Tathagata Paul and Schaik, {Andre van} and Arindam Ghosh and Thakur, {Chetan Singh}",

year = "2019",

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AU - Gupta, Sarthak

AU - Kumar, Pratik

AU - Paul, Tathagata

AU - Schaik, Andre van

AU - Ghosh, Arindam

AU - Thakur, Chetan Singh

PY - 2019

Y1 - 2019

N2 - Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

AB - Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

KW - analog CMOS integrated circuits

KW - computer network architectures

KW - low voltage integrated circuits

KW - neuromorphics

UR - https://hdl.handle.net/1959.7/uws:54568

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Low power, CMOS-MoS2 memtransistor based neuromorphic hybrid architecture for wake-up systems

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Keywords

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