Post-layout simulation of an ultra-low-power OTA using DTMOS input differential pair

In this paper, an ultra-low-power dynamic threshold voltage metal-oxide-semiconductor (DTMOS) amplifier is presented. In order to have a high open-loop gain and keep power consumption as low as possible, DTMOS differential pair at input stage technique has been used to improve the specifications of a conventional complementary metal-oxide-semiconductor (CMOS) amplifier such as power supply voltage and power consumption with a proper open-loop gain and unity gain bandwidth. The gain-stage compensation method has been used to overcome the stability problem. The proposed amplifier has been successfully validated and verified in TSMC 0.18 µm CMOS technology and post-layout simulated with Cadence Virtuoso. The post-layout simulation results show that the proposed operational transconductance amplifier (OTA) has 82.77 dB open-loop gain and total power consumption is about 163 nW with 0.4 V voltage supply which is suitable for low-power applications. In the final section in order to evaluate the OTA prefabrication performances, Monte Carlo and corner processes analysis have been performed. Acceptable output swing of 0.37 V is one of the additional features of the proposed OTA.