Hardware architectures for event-driven feature extraction algorithms

Abstract

Over the last decade, Neuromorphic Engineering (NE) has evolved into a prominent scientific discipline, advancing biologically inspired sensors, algorithms, hardware architectures, and processing techniques that emulate key operational principles of the human brain. Among these, the most notable innovation is the silicon retinas, commonly known as Dynamic Vision Sensor (DVS), which produce a stream of events in response to changes in luminosity in the light. Conventional frame-based processing techniques pose limitations in handling these streams of events, leading to the emergence of Event-Based (EB) processing techniques designed to manage the asynchronous stream of events generated by DVS sensors. In addition, the scientific community has witnessed a tremendous growth in EB vision solutions, where DVS have been deployed across diverse domains, including recognition, tracking, motion estimation, space do- main awareness, and space imaging.

The first part of the thesis proposes a reconfigurable hardware accelerator implemented on the Field Programmable Gate Array (FPGA) for the FEAST network. The novelty of the design lies in splitting the FEAST learning rule into two different sets of tasks and executing them independently in a time-multiplexed fashion, using a minimum number of hardware resources. The proposed hardware architecture, operated at 200 megahertz (MHz) clock frequency, can process 183⇥103 events/sec in training mode and 196⇥103 events/sec in inference mode.

The second part of the thesis examines the FPGA implementation of a reconfigurable hardware accelerator designed to support flexible Event Context (E C) computation of the FEAST algorithm. The architecture introduces a novel 1-D computing core, which operates as a broadcast structure utilising a loop unrolling mechanism that supports the T S and FEAST learning rule execution with minimum hardware utilisation. Additionally, the proposed flexible hardware offers configurability across a wide range of E C sizes, with radii ranging from 1 to 7. Compared to the first FEAST implementation, this architecture processes 3.95⇥ events.

The final part of the thesis explores the design of the first-ever multi-layer FEAST network and its FPGA implementation. The novelty of the design lies in the introduction of a 1-D computing core, which interleaves the FEAST layer computations without incurring additional hardware overhead. The proposed architecture achieves an event processing rate of 247⇥103 events/sec while the FEAST layers are configured with an E C size of 15 ⇥ 15.

Date of Thesis submission	2026
Original language	English
Awarding Institution	Western Sydney University
Sponsors	Australian Government Research Training Program Scholarship
Supervisor	Mark Wang (Supervisor), Ying Xu (Supervisor) & Andre van Schaik (Supervisor)